A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis
نویسندگان
چکیده
Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by 17.2% while using less than 24.5% capacitance resource compared with traditional symmetrical clock tree. Further, we also validated the algorithm in ASIC design.
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ورودعنوان ژورنال:
- IEICE Electronic Express
دوره 14 شماره
صفحات -
تاریخ انتشار 2017